Code generation, in particular for umts digital communications

ABSTRACT

One element in one of several orthogonal OVSF codes with at most 2 BM  elements is generated dynamically by deriving an intermediate word having (1) B least significant bits identical to the least significant bits in the reverse order of a word representing a code number SF=2 B  and (2) BM−B most significant bits having predetermined state. An AND circuit multiplies the bit in the intermediate word and a word representing a determined position of the element in the code produces a BM-bit product word. An EXCLUSIVE-OR operation on the bits of the product word generates the code element.

The present invention concerns in a general way the generation of codingsignals for code division multiple access (CDMA) digital communicationsin a base station or a mobile station of a system of simultaneoustransmissions at different bit rates, for example a cellularradiotelephone system. The invention concerns more particularly thegeneration of orthogonal variable spreading factor (OVSF) codesconforming to the Universal Mobile Telecommunications System (UMTS)standard in time division duplex (TDD) or frequency division duplex(FDD) mode, typically in the emitter or the receiver of a station overan uplink or a downlink.

For example, a TDD mode frame conforming to the UMTS mobile telephonystandard comprises timeslots of predetermined duration and eachincluding U simultaneous bursts of data, usually respectively assignedto U users. A code (channelisation code) for a burst allocated to agiven user is constituted of a sequence of SF code elements (chips)associated with each complex symbol to be transmitted, where U≦SF. Thecode elements are in non-return to zero (NRZ) code whose values are +1and −1. The length of each code, called the spreading factor, expressedas a number of code elements is equal to a power of 2 lying between 4=2²and 512=2⁹. The spreading factor may vary in a station, in particular asa function of the bit rate, also variable, requested for a user; forexample, a code for a given bit rate has a length equal to thehalf-length of a code for half the given bit rate.

The codes are traditionally generated by an iterative processreproducing a tree structure of the OVSF codes concerned, as shownschematically in FIG. 1, in which the set of codes concerned is denoted{C _(SF,NC)}_(SF=2) _(k) ,kε[0,9],NCε[0,SF−1]The iterative process is governed by the following equations:$\begin{matrix}{C_{1,0} = (1)} \\{C_{2,0} = \left( {1,1} \right)} \\{C_{2,1} = \left( {1,{- 1}} \right)} \\\ldots \\{{\left\{ C_{{SF},{NC}} \right\}_{{NC} \in {\lbrack{0,{{SF} - 1}}\rbrack}} = {\begin{pmatrix}C_{{SF},0} \\C_{{SF},1} \\\vdots \\C_{{SF},{{SF} - 2}} \\C_{{SF},{{SF} - 1}}\end{pmatrix} = \begin{pmatrix}{C_{{{SF}/2},0}C_{{{SF}/2},0}} \\{C_{{{SF}/2},0}{\overset{\sim}{C}}_{{{SF}/2},0}} \\\vdots \\{C_{{{SF}/2},{{{SF}/2} - 1}}C_{{{SF}/2},{{{SF}/2} - 1}}} \\{C_{{{SF}/2},{{{SF}/2} - 1}}{\overset{\sim}{C}}_{{{SF}/2},{{{SF}/2} - 1}}}\end{pmatrix}}},}\end{matrix}$in which {tilde over (C)}_(SF,sf) designates the code whose elementshave values opposite to those of the elements of the code C_(SF,sf):∀SF,∀sf ε[0,,SF−1], {tilde over (C)}_(SF,sf)=−C_(SF,sf)

In the emitter at the radio interface of a station, a spreadingmodulator processes the successive complex symbols leaving a QPSK phasemodulator to produce the code associated with a user and modulating thereal and imaginary components of each symbol to be applied to ascrambler before being filtered, amplified and transposed in frequency.For each user, a code is written in a code memory at the beginning of acall with that user and may be modified as a function of a codemodification request during the call. Thus two memories are provided: atable of the correspondences between the user identification numbers andthe code numbers and a table of the correspondences between the codenumbers and the codes. Typically, for at least 2⁹=512 codes each having512 code elements, the capacity of the second memory must be at least${{\sum\limits_{B = 2}^{B = 9}2^{2B}} = {349520\quad{bits}}},$i.e. 43 kbytes.

Thus the codes must be generated before they are used and necessitate amemory space for storing them.

The invention aims to, obviate these drawbacks by generating codesdirectly as and when calls proceed in a station, without using anysecond memory establishing the correspondence between a code number anda code, i.e. without memorizing the codes.

Accordingly a device according to the invention for generating at mostSFM=2^(BM) orthogonal codes each comprising at most SFM code elements,BM being an integer, generates a code element thanks to the followingmeans. The device receives a word representative of a determinedposition of the code element in a code, a word representative of thecode number designating the code from SF=2^(B) possible codes with SFelements and a word representative of a number allocated to the numberSF of elements of the code, B being an integer such that B≦BM. Thedevice comprises logic means for supplying an BM-bits intermediate wordin which B less significant bits are the B less significant bits in thereverse order in the code number word and BM−B more significant bits areall in a predetermined state, means for respectively multiplying thebits having the same rank in the intermediate word and the position wordto produce a BM-bits product word, and means for applying anEXCLUSIVE-OR operation to all the bits of the product word in order togenerate the code element.

Thus the elements of a code are generated dynamically by logic meanswith no code memory. More generally, the codes are generated dynamicallyby the device of the invention in response to permanent requests at highfrequency associated with traffic channels occupied by calls between afixed or mobile station including the device and another mobile or fixedstation.

The device of the invention advantageously has a relatively small sizeby virtue of microcircuit design and may be included more than once inthe same station in order to generate a plurality of orthogonal codessimultaneously and in an independent fashion.

According to a preferred embodiment, the logic means comprises means forreversing the order of the bits of the code number word into a reversedword, means for determining the difference BM−B, and means for shiftingby BM−B positions toward the less significant bits the B moresignificant bits of the reversed word in order to form the intermediateword with bits in the predetermined state as BM−B more significant bitsand with the B more significant bits of the reversed word as B lesssignificant bits.

According to a special embodiment directed towards the UMTS standardBM=9, and B=0 and B=1 are prohibited values, and the differencedetermining means consists in means for inverting the state of the bitsof the word representative of the number allocated to the number of codeelements into a shift parameter word to be applied to the shiftingmeans.

Other features and advantages of the present invention will become moreclearly apparent on reading the following description of a plurality ofpreferred embodiments of the invention with reference to thecorresponding appended drawings, in which:

FIG. 1 is a tree diagram of the prior art iterative OVSF orthogonalcodes process; and

FIG. 2 is a block diagram of an OVSF orthogonal code generation deviceaccording to the invention.

The code generation device according to the invention is included in aspreading modulator of the emitter for example of a base station andaims to generate codes including a maximum of SFM bits. For the UMTSstandard, the maximum number of bits SFM is equal to 512=2⁹⁼² ^(BM).

In the remainder of the description, a binary word M comprising BM bitsis designated by the bits M_(BM−1), M_(BM−2), . . . M₂, M₁, M₀; M_(BM−1)and M₀ being the most significant bit and the least significant bit ofthe word M. The logic functions defined hereinafter are implemented inpositive logic by way of example.

As shown in FIG. 2, the code generation device 1 essentially comprisesthree data input ports through which it receives three binary wordsrepresentative of integer numbers PC, B and NC that are sufficient togenerate a binary code element EC, finally converted into non-return tozero (NRZ) code.

The first word is representative of a determined position PC of the codeelement EC in a given code (channelisation code) and is provided by atimebase in the modulator. The position of a code element beingcomprised between 0 and the length SF−1 of the code, and more generallyable to vary from 0 to SFM−1=2⁹−1=511, the word PC comprises BM=9 bitsPC_(BM−1) to PC₀.

The second and third words are provided by a correspondence tableequivalent to the first memory cited above in the modulator in responseto the identification number of a given user. The second word isrepresentative of the number NC of the given code that designates thecode from the SF=2^(B) possible codes with SF elements and which istherefore from 0 to SF−1. Since SF is at most equal to SFM, the numberof bits NC_(BM−1) to NC₀ of the word NC also comprises BM=9 bits and thenumber may take 2^(BM)=512 values. The third word is representative ofthe spreading factor SF of the given code, equal to the number ofelements in the given code, where SF=2^(B) and the integer B such thatB≦BM.

In fact, the number of bits in the third word is at most equal to themaximum number of bits necessary for designating the BM spreadingfactors SF, i.e. for successively numbering the BM spreading factorsrespectively equal to the lengths of the codes varying from 2 to 2^(BM)in successive powers of 2. The number of bits of the third word istherefore equal to the integer portion of log₂(2×BM−1). The two columnsof the next correspondence table 1 establish the correspondence of the4=integer part (log₂ 17) bits B₃, B₂, B₁ and B₀ of the third word andthe spreading factor SF for BM=9: TABLE 1 SF = 2^(B) B₃, B₂, B₁, B₀ D =BM − B D₃, D₂, D₁, D₀ 1 0000 9 1001 2 0001 8 1000 4 0010 7 0111 8 0011 60110 16 0100 5 0101 32 0101 4 0100 64 0110 3 0011 128 0111 2 0010 2561000 1 0001 512 1001 0 0000

It is shown that the code element EC to be generated is deduced from thefollowing logic equation:EC=XOR(AND(SHR(REV(NC,BM),BM-SF),PC)).

REV, SHR, AND and XOR designate logic operations that are respectivelyeffected by logic circuits 2, 3, 4 and 5 included in the code generationdevice 1, as shown in FIG. 2.

The circuit 2 implements the REV (REVerse) function in order to reversethe order of the bits NC₀ to NC_(BM−1) of the word representative of thecode number NC. The circuit 2 supplies a reversed word NC′ whose bitsNC′_(BM−1) to NC′₀ are respectively identical to the bits NC₀ toNC_(BM−1), as indicated in detail hereinafter for BM=9: NC (NC₈, NC₇,NC₆, NC₅, NC₄, NC₃, NC₂, NC₁, NC₀) NC′ (NC′₈, NC′₇, NC′₆, NC′₅, NC′₄,NC′₃, NC′₂, NC′₁, NC′₀) = (NC₀, NC₁, NC₂, NC₃, NC₄, NC₅, NC₆, NC₇, NC₈)

The circuit 3 is a programmable rightward shift register for shifting tothe right, i.e. toward the less significant bits, the more significantbits of the reversed word NC′. The circuit 3 implements an SHR (SHiftRight) function in which the shift is equal to the difference BM−Bproduced by a difference determination circuit 31. To the circuit 31 isapplied the word B₃,B₂,B₁,B₀ with 4=integer part of log₂(2BM−1) bitsrepresentative of the exponent B of the power of 2 equal to thespreading factor SF, i.e. the number B of the spreading factor from theBM spreading factors, i.e. from the BM stages of the tree structureshown in FIG. 1. The numbers B from 1 to BM of spreading factors areordered in increasing order of the spreading factors SF.

The circuit 31 calculates the difference BM−B to supply a shiftparameter word on 4 bits D₃, D₂, D₁, D₀, as indicated in the third andfourth columns of the above table 1, to be applied as shift parameters Dto the circuit 3. The circuit 3 supplies an intermediate word NC″ withBM bits NC″_(BM−1) to NC″₀ whose B less significant bits are the B moresignificant bits of the reversed word NC′ and therefore the B lesssignificant bits in the reverse order in the word representative of thecode number NC and whose BM−B more significant bits are bits in thepredetermined binary state “0”, in accordance with the following tablefor BM=9: D = (NC″₈, NC″₇, NC″₆, NC″₅, NC″₄, B-1 BM − B NC″₃, NC″₂,NC″₁, NC″₀) 0000 1000 (0, 0, 0, 0, 0, 0, 0, 0, NC′₈) = (0, 0, 0, 0, 0,0, 0, 0, NC₀) 0001 0111 (0, 0, 0, 0, 0, 0, 0, NC′₈, NC′₇) = (0, 0, 0, 0,0, 0, 0, NC₀, NC₁) 0010 0110 (0, 0, 0, 0, 0, 0, NC′₈, NC′₇, NC′₆) = (0,0, 0, 0, 0, 0, NC₀, NC₁, NC₂) 0011 0101 (0, 0, 0, 0, 0, NC′₈, NC′₇,NC′₆, NC′₅) = (0, (0, 0, 0, 0, NC₀, NC₁, NC₂, NC₃) 0100 0100 (0, 0, 0,0, NC′₈, NC′₇, NC′₆, NC′₅, NC′₄) = (0, 0, 0, 0, NC₀, NC₁, NC₂, NC₃, NC₄)0101 0011 (0, 0, 0, NC′₈, NC′₇, NC′₆, NC′₅, NC′₄, NC′₃) = (0, 0, 0, NC₀,NC₁, NC₂, NC₃, NC₄, NC₅ ) 0110 0010 (0, 0, NC′₈, NC′₇, NC′₆, NC′₅, NC′₄,NC′₃, NC′₂) = (0, 0, NC₀, NC₁, NC₂, NC₃, NC₄, NC₅, NC₆) 0111 0001 (0,NC′₈, NC′₇, NC′₆, NC′₅, NC′₄, NC′₃, NC′₂, NC′₁) = (0, NC₀, NC₁, NC₂,NC₃, NC₄, NC₅, NC₆, NC₇) 1000 0000 (NC′₈, NC′₇, NC′₆, NC′₅, NC′₄, NC′₃,NC′₂, NC′₁, NC′₀) = (NC₀, NC₁, NC₂, NC₃, NC₄, NC₅, NC₆, NC₇, NC₈)

In practice, the UMTS standard prohibits the use of values SF≦2 and B=0and B=1, i.e. the use of the first stage with two codes in the treestructure from FIG. 1. The spreading factor SF has only BM−1=8 possiblevalues 2²=4 to 2⁹=2^(BM). The number B−2 of the spreading factor maythen vary from 0 to BM−2 so that the word representative of the numberof the spreading factor SF comprises only 3=integer part log₂(2.8−1)bits. The spreading factor number word, thus with 3 bits B₂,B₁,B₀,instead of 4 bits, is applied to the input port of the circuit 31.Instead of establishing the difference D=BM−B directly, as before, thecircuit 31 preferably executes a function equivalent to this differenceby determining the “1”'s complement, i.e. by inverting the state of eachbit of the incoming word of 3 bits in accordance with the first twocolumns of the following table whose third column indicates thecorresponding intermediate word NC″ at the output of the shift circuit3: (NC″₈, NC″₇, NC″₆, NC″₅, NC″₄, B-2 D NC″₃, NC″₂, NC″₁, NC″₀) 000 111(0, 0, 0, 0, 0, 0, 0, NC′₈, NC′₇) = (0, 0, 0, 0, 0, 0, 0, NC₀, NC₁) 001110 (0, 0, 0, 0, 0, 0, NC′₈, NC′₇, NC′₆) = (0, 0, 0, 0, 0, 0, NC₀, NC₁,NC₂) 010 101 (0, 0, 0, 0, 0, NC′₈, NC′₇, NC′₆, NC′₅) = (0, 0, 0, 0, 0,NC₀, NC₁, NC₂, NC₃) 011 100 (0, 0, 0, 0, NC′₈, NC′₇, NC′₆, NC′₅, NC′₄) =(0, 0, 0, 0, NC₀, NC₁, NC₂, NC₃, NC₄) 100 011 (0, 0, 0, NC′₈, NC′₇,NC′₆, NC′₅, NC′₄, NC′₃) = (0, 0, 0, NC₀, NC₁, NC₂, NC₃, NC₄, NC₅) 101010 (0, 0, NC′₈, NC′₇, NC′₆, NC′₅, NC′₄, NC′₃, NC′₂) = (0, 0, NC₀, NC₁,NC₂, NC₃, NC₄, NC₅, NC₆) 110 001 (0, NC′₈, NC′₇, NC′₆, NC′₅, NC′₄, NC′₃,NC′₂, NC′₁) = (0, NC₀, NC₁, NC₂, NC₃, NC₄, NC₅, NC₆, NC₇) 111 000 (NC′₈,NC′₇, NC′₆, NC′₅, NC′₄, NC′₃, NC′₂, NC′₁, NC′₀) = (NC₀, NC₁, NC₂, NC₃,NC₄, NC₅, NC₆, NC₇, NC₈)

The circuit 4 combines two by two respectively the BM bits of weight 0to BM−1 in the intermediate word NC″ and the BM bits of weight 0 to BM−1in the word representative of the position PC of the code element to begenerated, using BM respective AND gates with two inputs. The BM−B firstoperations AND produce more significant bits PC′_(BM−)1 to PC′_(BM−B) ofan intermediate product in the predetermined state “0”, and theremaining B operations AND produce less significant bitsPC′_(BM−B−1)=(NC″_(BM−B−1)×PC_(BM−B−1)) to PC′₀=(NC″₀×PC₀) of theintermediate product.

The circuit 5 determines a parity bit BP of the intermediate productequal to the code element EC in binary to be generated. The parity bitBP is in the state “1” when the number of “1” bits in the intermediateproduct word PC′_(BM−1) to PC′₀ is odd and the state “0” when theaforementioned number of “1” bits is even. The circuit 5 includes anEXCLUSIVE-OR gate with BM inputs for applying the EXCLUSIVE-OR operationto 3 bits of the intermediate result word, that is to say:BP=PC′ _(BM−1) ⊕PC′ _(BM−2)⊕ . . . ⊕PC′₂⊕PC′₁⊕PC′₀.

Finally, the code generation device 1 comprises a binary to non-returnto zero code converter 6 for converting the binary state “0” or “1” ofthe parity bit BP into the generated code element EC “1” or “−1” to beapplied to the spreading data input of the scrambler referred to in thepreamble of the description.

In practice, the code generation device 1 is designed in the form of aprogrammable logic circuit or an application-specific integrated circuit(ASIC) logic circuit. It constitutes a circuit of very small size inorder for a plurality of devices 1 to be installed in parallel in afixed or mobile station of a UMTS cellular radiotelephone network togenerate simultaneously OVSF orthogonal codes.

1-4. (canceled)
 5. A device for generating at most SFM=2^(BM) orthogonalcodes each comprising at most SFM code elements, BM being an integer,said device being adapted to receive (a) position word representative ofa determined position of said code element in a code, (b) a code numberword representative of a code number designating said code from SF=2^(B)possible codes with SF elements and (c) a word representative of anumber allocated to the number SF of elements of said code, B being aninteger such that B≦BM, and said device comprising processor circuitryfor (a) deriving a BM-bit intermediate word, the B least significantbits of intermediate word being the least B significant bits in thereverse order of the code number word and the BM−B most significant bitsof intermediate word being all in a predetermined state, (b) forrespectively multiplying the bits having same ranks in said intermediateword and said position word to produce a BM-bit product word, and (c)for generating said code element by applying an EXCLUSIVE-OR operationto all the bits of said product word.
 6. The apparatus of claim 5,wherein the processor circuitry is arranged for (a) reversing the orderof the bits of said code number word into a reversed word, (b)determining the difference BM−B, (c) shifting the B most significantbits of said reversed word by BM−B positions toward the leastsignificant bits, and (d) forming said intermediate word with bits inthe predetermined state as the BM−B most significant bits and with the Bmost significant bits of said reversed word as the B least significantbits.
 7. The device of claim 6, wherein the processor circuitry isarranged for forming the intermediate word by shifting the B mostsignificant bits of said reversed word by BM−B positions toward theleast significant bits.
 8. A device according to claim 6, wherein BM=9and B=0 and B=1 are prohibited values, and said processor circuitry isarranged for determining the difference by inverting the state of thebits of said word representative of the number allocated to said numberof code elements into a shift parameter word for causing said shiftingoperation.
 9. A device according to claim 5, wherein the processorcircuitry is arranged for performing a binary-non-return to zerooperation on the output of said EXCLUSIVE-OR operation.
 10. A basestation for code division multiple access digital communicationsincluding a code generation device for generating at most SFM=2_(BM)orthogonal codes, each comprising at most SFM code elements, BM being aninteger, said code generation device being arranged to receive (a) aposition word representative of a determined position of said codeelement in a code, (b) a code number word representative of a codenumber designating said code from SF=2^(B) possible codes with SFelements and (c) a word representative of a number allocated to thenumber SF of elements of said code, B being an integer such that B≦BM,and said code generation device comprising processing circuitry for (a)deriving a BM-bit intermediate word such that the B least significantbits of the intermediate word are the B least significant bits in thereverse order in the code number word and the BM−B most significant bitsof the intermediate word all have predetermined state, (b) respectivelymultiplying the bits having the same ranks in said intermediate word andsaid position word to produce a BM-bit product word, and (c) generatingsaid code element by applying an EXCLUSIVE-OR operation to all the bitsof said product word.
 11. A method of generating at most SFM=2^(BM)orthogonal codes, each including at most SFM code elements, BM being aninteger, said method being performed in response to: (a) position wordrepresentative of a determined position of said code element in a code,(b) a code number word representative of a code number designating saidcode from SF=2^(B) possible codes with SF elements, and (c) a wordrepresentative of a number allocated to the number SF of elements ofsaid code, B being an integer such that B≦BM, the method comprising: (a)deriving a BM-bit intermediate word, the B least significant bits ofintermediate word being the least B significant bits in the reverseorder of the code number word and the BM−B most significant bits ofintermediate work being all in a predetermined state, (b) respectivelymultiplying the bits having same ranks in said intermediate word andsaid position word to produce a BM-bit product word, and (c) generatingsaid code element by applying an EXCLUSIVE-OR operation to all the bitsof said product word.
 12. A method of generating at most SFM=2^(BM)orthogonal codes used in code division multiple access digitalcommunications, each code having at most SFM code elements, BM being aninteger, said method being performed in response to (a) a position wordrepresentative of a determined position of said code element in ac ode,(b) a code number word representative of a code number designating saidcode from SF=2^(B) from possible codes with SF elements and (c) a wordrepresentative of a number allocated to the number SF of elements ofsaid code, B being an integer such that B≦BM, and said method comprising(a) deriving an BM-bit intermediate word in which the B leastsignificant bits of the intermediate word are the B least significantbits in the reverse order of the code number word and the BM−B mostsignificant bits of the intermediate word all have a predeterminedstate, (b) producing a BM-bit product word by respectively multiplyingthe bits having the same ranks in said intermediate word and saidposition word to produce, and (c) generating one of said code elementsby applying an EXCLUSIVE-OR operation to all the bits of said productword.
 13. Performing the method of claim 12 at a base station. 14.Performing the method of claim 12 at a mobile station.
 15. The method ofclaim 12 further including reversing the order of the bits of said codenumber word into a reversed word, determining the difference BM−B,forming said intermediate word with bits in the predetermined state asthe BM−B most significant bits and with the B most significant bits ofsaid reversed word as the B least significant bits.
 16. The method ofclaim 15, wherein the intermediate word is formed by shifting the B mostsignificant bits of said reversed word by BM−B positions toward theleast significant bits.
 17. The method of claim 12 further includingreversing the order of the bits of said code number word into a reversedword, determining the difference BM−B, shifting the B most significantbits of said reversed word by BM−B positions toward the leastsignificant bits; and forming said intermediate word with bits in thepredetermined state as the BM−B most significant bits and with the Bmost significant bits of said reversed word as the B least significantbits, wherein the intermediate word is formed by the B most significantbits of said reversed word.
 18. The method of claim 16, wherein BM=9,and B=0 and B=1 are prohibited values, and said difference is determinedby inverting the state of the bits of said word representative of thenumber allocated to said number of code elements into a shift parameterword on which the shifting step is performed.
 19. The method of claim12, further comprising performing a binary-non-return to zero conversionon the code elements resulting from the said EXCLUSIVE-OR operation.